Delay Propagation of a CMOS Inverter Using the Nexp Transistor Model

Abstract

This paper presents an analytical model for the delay propagation of a CMOS Invert circuit. In this paper the Nexp transistor model is considered as a way of granting the accuracy of results in the characterization of submicron CMOS circuits. The analytical model proposed is valid for a ramp input, and takes into account all the operation regions of the transistor and take into account the influence of the gate-to-drain capacitance. An application example considering the use of the model for the evaluation of the delay associated to the CMOS inverter is considered. The validity of the results obtained with analytical model of a 1.8V SMIC018 CMOS inverter is checked against Hspice simulation of the circuit.